SPARC architecture specifics
32 integer registers are supported r0..r31. The registers can be 32 or 64-bitdepending on the processor you are executing on. When r0 is read a value of zerois always returned. When r0 is used as a destination register the result of the operationis ignored.
sp = r14
fp = r30
On the SPARC processor alias names are provided to correspond to the typical SPARCassembly code.
32 floating point registers are supported f0..f31.
The SPARC is a bit unusual in that it supports separate single and double precisionregisters. A double precision register overlaps two single precision registers. Thisassembler does not support this mode as it is not portable. In this assembler bothfloating point single and double precision registers are numbers 0..31. This is unlikenative SPARC assembly where double precision registers are only even numbered registers.Some instructions do exist that access SPARC single precision registers. These instructionsexist solely to support the use of a double precision only register file.
In this assembler you should not use floating point register f0. This is usedby some of the instructions for conversion between single and double precision. Thisallows the assembler to show a single floating point double precision register file.The f0 register is still used for floating point function returns, but this usagedoes not conflict with the automatic conversion of single precision numbers.
Obviously given this implementation, double precision operations are smaller sincea conversion instruction does not need to be generated.
Instructions
| Mnemonic | Operand types | Function |
| ldd64 | reg, mem | Load a 64-bit integer from memory into a register pair (reg, reg+1). reg must be an even numbered register. The first 32-bit memory word is loaded into the first register. |
| std64 | mem, reg | Store a 64-bit integer to memory from a register pair (reg, reg+1). reg must be an even numbered register. 32-bits is taken from each register to comprise the 64-bit memory data. |
| flds32 | freg, mem | Load a single precision memory value into a single precision register. You should be using flds. |
| fsts32 | mem, freg | Store a single precision register value into memory in single precision form. You should be using fsts. |
| flddua | freg, mem | Load an unaligned double precision memory value into a double precision register. This generates two single precision loads. |
| fstdua | mem, freg | Store an unaligned double precision memory value from a double precision register. This generates two single precision stores. |
| addcc | regD, regS1, regS2 regD, regS1, imm | Add regS1 to regS2/imm and store the result into regD and set the condition codes. |
| addC | regD, regS1, regS2 regD, regS1, imm | Add carrying regS1 to regS2/imm and store the result into regD. |
| addCcc | regD, regS1, regS2 regD, regS1, imm | Add carrying regS1 to regS2/imm and store the result into regD and set the condition codes. |
| subcc | regD, regS1, regS2 regD, regS1, imm | Subtract regS2/imm from regS1 and store the result into regD and set the condition codes. |
| subC | regD, regS1, regS2 regD, regS1, imm | Subtract borrowing regS2/imm from regS1 and store the result into regD. |
| subCcc | regD, regS1, regS2 regD, regS1, imm | Subtract borrowing regS2/imm from regS1 and store the result into regD and set the condition codes. |
| mul32s | regD, regS1, regS2 regD, regS1, imm | 32-bit signed Multiply of regS1 by regS2/imm and store the result into regD. |
| mul32u | regD, regS1, regS2 regD, regS1, imm | 32-bit Multiply unsigned regS1 by regS2/imm and store the result into regD. |
| div32s | regD, regS1, regS2 regD, regS1, imm | 32-bit signed divide of regS1 by regS2/imm and store the result into regD. |
| div32u | regD, regS1, regS2 regD, regS1, imm | 32-bit unsigned divide of regS1 by regS2/imm and store the result into regD. |
| orcc | regD, regS1, regS2 regD, regS1, imm | Perform a bitwise logical or of regS1 with regS2/imm and store the result into regD and set the condition codes. |
| andcc | regD, regS1, regS2 regD, regS1, imm | Perform a bitwise logical and of regS1 with regS2/imm and store the result into regD and set the condition codes. |
| andncc | regD, regS1, regS2 regD, regS1, imm | Perform a bitwise logical and of regS1 with the bitwise logical not of regS2/imm and store the result into regD and set the condition codes. |
| save | none regD, regS1, regS2 regD, regS1, imm | Create a new register window. |
| restore | none regD, regS1, regS2 regD, regS1, imm | Restore the previous register window. |
| retl | none | Return from leaf procedure |
| fstod | fregD, fregS | Convert a single precision value in single precision register fregS to a double precision value in fregD. |
| fdtos | fregD, fregS | Convert a double precision value in fregS to a single precision value in single precision register fregD. |
| sethi | reg, imm | Set the high 22 bits of register reg with the immediate value. The low bits are zeroed. |
| wry | reg imm | Write reg/imm to the Y register. |
| rdy | reg | Read the Y register into reg |
| wrasi | reg imm | Write reg/imm to the ASI register. |
| flushw | Flush the register windows to memory. | |
| cas32 | regD, regS1, regS2 | 32-bit compare and swap |
| rdtick | reg | Read the TICK register into reg. |
| bpos | label [, pt | pn ] | Branch if positive. |
| bneg | label [, pt | pn ] | Branch if negative. |
| bo | label [, pt | pn ] | Branch if overflow. |
| bno | label [, pt | pn ] | Branch if not overflow. |
| bc | label [, pt | pn ] | Branch if carry. |
| bnc | label [, pt | pn ] | Branch if no carry. |
| brz | reg, label | Branch if register reg(64-bit) is zero. |
| brnz | reg, label | Branch if register reg(64-bit) is not zero. |
| brlz | reg, label | Branch if register reg(64-bit) is less than zero. |
| brgez | reg, label | Branch if register reg(64-bit) is greater than or equal to zero. |
| brgz | reg, label | Branch if register reg(64-bit) is greater than zero. |
| brlez | reg, label | Branch if register reg(64-bit) is less than or equal to zero. |
| move | regD, regS regD, imm | Conditional move of regS/imm to regD if equal. |
| movne | regD, regS regD, imm | Conditional move of regS/imm to regD if not equal. |
| movl | regD, regS regD, imm | Conditional move of regS/imm to regD if less than. (signed) |
| movge | regD, regS regD, imm | Conditional move of regS/imm to regD if greater than or equal. (signed) |
| movg | regD, regS regD, imm | Conditional move of regS/imm to regD if greather than. (signed) |
| movle | regD, regS regD, imm | Conditional move of regS/imm to regD if less than or equal. (signed) |
| movlu | regD, regS regD, imm | Conditional move of regS/imm to regD if less than. (unsigned) |
| movgeu | regD, regS regD, imm | Conditional move of regS/imm to regD if greater than or equal. (unsigned) |
| movgu | regD, regS regD, imm | Conditional move of regS/imm to regD if greather than. (unsigned) |
| movleu | regD, regS regD, imm | Conditional move of regS/imm to regD if less than or equal. (unsigned) |
| movpos | regD, regS regD, imm | Conditional move of regS/imm to regD if positive. (signed) |
| movneg | regD, regS regD, imm | Conditional move of regS/imm to regD if negative. (signed) |
| movo | regD, regS regD, imm | Conditional move of regS/imm to regD if overflow. (signed) |
| movno | regD, regS regD, imm | Conditional move of regS/imm to regD if no overflow. (signed) |
| movc | regD, regS regD, imm | Conditional move of regS/imm to regD if carry. (unsigned) |
| movnc | regD, regS regD, imm | Conditional move of regS/imm to regD if no carry. (unsigned) |
| movrz | regD, regS1, regS2 | Conditional register move of regS2 to regD if register regS1 zero. |
| movrnz | regD, regS1, regS2 | Conditional register move of regS2 to regD if register regS1 not zero. |
| movrlz | regD, regS1, regS2 | Conditional register move of regS2 to regD if register regS1 less than zero. |
| movrgez | regD, regS1, regS2 | Conditional register move of regS2 to regD if register regS1 greater than or equal to zero. |
| movrgz | regD, regS1, regS2 | Conditional register move of regS2 to regD if register regS1 greater than zero. |
| movrlez | regD, regS1, regS2 | Conditional register move of regS2 to regD if register regS1 less than or equal to zero. |